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Esmaeili M R, Zahiri S H, Razavi S M. An efficient CAD tool for High-Level Synthesis of VLSI digital transformers. JSDP 2021; 18 (3) :3-18
URL: http://jsdp.rcisp.ac.ir/article-1-983-en.html
URL: http://jsdp.rcisp.ac.ir/article-1-983-en.html
University of Birjand
Abstract: (2097 Views)
Digital transformers are considered as one of the digital circuits being widely used in signal and data processing systems, audio and video processing, medical signal processing as well as telecommunication systems. Transforms such as Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT) and Fast Fourier Transform (FFT) are among the ones being commonly used in this area. As an illustration, the DCT is employed in compressing the images. Moreover, the FFT can be utilized in separating the signal spectrum in signal processing systems as fast as possible. The DWT is used in separating the signal spectrum in a variety of applications from signal processing to telecommunication systems, as well.
In order to build a VLSI circuit, several steps have to be taken from chip design to final construction. The first step in the synthesis of the integrated circuits is called high-level synthesis (HLS), in which a structural characteristic is obtained from a behavioral or algorithmic description. The resulting structural characteristic is equivalent to the one being considered in the behavioral description and it somehow represents the method for implementing the behavioral description as a result several structural descriptions could be implementable for each behavioral description. Therefore, depending on the intended use, the characteristic will be selected that outperforms the others. The main purpose of the HLS is to optimize the power consumption, the chip occupied area and delayed and is fulfilled by selecting the appropriate number of operating units and how they are implemented to the operators. This is generally accomplished through a graph analysis called the data flow graph (DFG) which is a graphical representation of the type and how the operators connect. In the DFG, each node is equivalent to an operator while the edges represent the relationship between these operators.
Experience has proved that if the level of design optimization is high, in addition to higher efficiency, the design time will be lower, which is why the researchers are far more interested in optimization at higher levels of design than the lower levels. The complex, extensive, and discrete nature of the HLS problems have been ranked them among the most complex problems in VLSI circuits engineering. Bearing this mind, using meta-heuristic and Swarm intelligence methods to solve high-level synthesis projects seems to be a favored option. In this paper, a heuristic method called Moth-Flame Optimization (MFO) has been used to solve the HLS problem in the design of digital transformer to find the optimal response. The MFO is a population-based heuristic algorithm that optimizes the problems using the laws of nature. The leading notion behind the MFO algorithm inspired from the moths’ movements and their instinctive navigation during the night. In the MFO algorithm, the moths are like chromosomes in the GA and like the particles in the PSO algorithm. In order to compare and prove the efficiency of the proposed method, it was applied on the test data with the GA-based method separately but with the same initial conditions. The comparative results along with the results of the GA-based method demonstrated that the proposed method exhibits a higher ability to provide the appropriate hardware structure and high-level synthesis of various types of transformers. Another outstanding feature of the proposed method is its high speed of finding an optimal response with an average of more than 20% greater than the GA based method.
Keywords: High-Level Synthesis, Datapath, Digital Transformers, Meta-heuristic Algorithm, MFO Algorithm
Type of Study: Research |
Subject:
Paper
Received: 2019/03/5 | Accepted: 2020/01/22 | Published: 2022/01/20 | ePublished: 2022/01/20
Received: 2019/03/5 | Accepted: 2020/01/22 | Published: 2022/01/20 | ePublished: 2022/01/20
References
1. [1] M. C. Bhuvaneswari, Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems. Springer, India 2015. [DOI:10.1007/978-81-322-1958-3] [PMCID]
2. [2] S. Das, R. Maity, N. P. Maity, "VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach," Circuits, Systems, and Signal processing, vol. 37, no. 4, pp. 1575-1593, April 2018. [DOI:10.1007/s00034-017-0609-3]
3. [3] D. Thomas, E. Lagnese, R.Walker, J. Nestor, J. Rajan, and R. Blackburn, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer, 1990. [DOI:10.1007/978-1-4613-1519-3]
4. [4] D. S. Harish Ram, M. C. Bhuvaneswari, S. S. Prabhu, "A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths," VLSI Design, vol. 2012, 2012. [DOI:10.1155/2012/273276]
5. [5] X. Tang, T. Jiang, A. Jones, P. Banerjee, "Behavioral synthesis of data-dominated circuits for minimal energy implementation," in Proc. of 18th the International Conference on VLSI Design,Jan. 2005, pp.3-7.
6. [6] N. Chabini, W. Wolf, "Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints," IEEE Transactions on VLSI Systems, vol. 13, no. 10, pp. 1113-1126, 2005. [DOI:10.1109/TVLSI.2005.859482]
7. [7] S. P. Mohanty, N. Ranganathan, S. K. Chappidi, "ILP models for simultaneous energy and transient power minimization during behavioral synthesis," ACM Transaction on Design Automation of Electronic Systems, vol. 11, no. 1, pp. 186-212, 2006. [DOI:10.1145/1124713.1124725]
8. [8] W. T. Shiue, "Peak power minimization using novel scheduling algorithm based on an ILP model," in Proc. of the 10th NASA Symposium on VLSI Design, 2002.
9. [9] A. Kumar, M. Bayoumi, "Multiple voltage-based scheduling methodology for low power in the high level synthesis," in Proc. of the International Symposium on Circuits and Systems (ISCAS), 1999, pp. 371-379.
10. [10] A. K. Murugavel and N. Ranganathan, "A game theoretic approach for power optimization during behavioral synthesis," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1031-1043, 2003. [DOI:10.1109/TVLSI.2003.819566]
11. [11] R. K. Brayton, R. Camposano, G. De Micheli, R. Otten, J. van Eijndhoven, "The Yorktown silicon compiler system," in Silicon Compilation, D. D. Gajski, Ed. Reading, MA: Addison-Wesley, pp. 204-310, 1988.
12. [12] O. V. Nepomnyashchiy, I. V. Ryjenko, V. V. Shaydurov, N. Y. Sirotinina A. I. Postnikov, "The VLSI High-Level Synthesis for Building Onboard Spacecraft Control Systems," in Anisimov K. et al. (eds) Proceedings of the Scientific-Practical Conference "Research and Development 2016", Springer, Cham, 2018, pp. 229-238. [DOI:10.1007/978-3-319-62870-7_25]
13. [13] R. Gopalan, C. Gopalakrishnan, S. Katkoori, "Leakage power driven behavioral synthesis of pipelined datapaths," in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 167-172, 11-12May 2005.
14. [14] S. P. Mohanty, R. Velagapudi, E. Kougianos, "Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits," in Proc. of the Conference on Design, Automation and Test in Europe, 6-10 March 2006, pp. 1191-1196. [DOI:10.1109/DATE.2006.244046]
15. [15] F. Su, K. Chakrabarty, "Unified high-level synthesis and module placement for defecttolerant microfluidic biochips," in Proc. of the 42nd Annual Conference on Design automation, 13-17 June 2005, pp. 825-830. [DOI:10.1145/1065579.1065797] [PMID]
16. [16] S. Devadas, A. R. Newton, "Algorithms for hardware allocation in data path synthesis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 7, pp. 768-781, 1989. [DOI:10.1109/43.31534]
17. [17] J. A. Nestor, G. Krishnamoorthy, "SALSA: A new approach to scheduling with timing constraints," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1107-1122, 1993. [DOI:10.1109/43.238604]
18. [18] G. Krishnamoorthy, J. A. Nestor, "Data path allocation using extended binding model," in Proc. 29nd ACM/IEEE Design Automation Conf., 8-12 June 1992, pp. 279-284.
19. [19] T. A. Ly, J. T. Mowchenko, "Applying simulated evolution to high level synthesis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 3, pp. 389-409, 1993. [DOI:10.1109/43.215002]
20. [20] S. Lucia, D. Navarro, O. Lucia, P. Zometa, R. Findeisen, "Optimized FPGA Implementation of Model Predictive Control for Embedded Systems Using High-Level Synthesis Tool," IEEE Trans. on Industrial Informatics, vol. 14, no. 1, pp. 137-145, Jan. 2018. [DOI:10.1109/TII.2017.2719940]
21. [21] G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York 1994.
22. [22] R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. Comput. -Aided Des., vol. 10, pp. 85-93, 1991. [DOI:10.1109/43.62794]
23. [23] P. G. Paulin, J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASICs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 6, pp. 661-679, 1989. [DOI:10.1109/43.31522]
24. [24] S. Gupta, S. Katkoori, "Force-directed scheduling for dynamic power optimization," in Proc. of the IEEE Computer Society Annual Symposium on VLSI, 25-26 April 2002, pp. 68-73.
25. [25] S. H. Gerez, Algorithms for VLSI Design Automation. Wiley, 2004.
26. [26] S. Katkoori, R. Vemuri, "Scheduling for low power under resource and latency constraints," in Proc. of the IEEE International Symposium on Circuits and Systems, 28-31 May 2000, pp. 53-56.
27. [27] A. C. Parker, J. T. Pizarro, M. Mlinar, "Maha: A program for datapath synthesis," in Proc. 23rd ACM/IEEE Design Automation Conf., 29 June- 2 July 1986, pp. 461-466. [DOI:10.1109/DAC.1986.1586129]
28. [28] M. McFarland, T. J. Kowalski, "Incorporating bottom-up design into high-level synthesis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 9, pp. 938-950, Sep. 1990. [DOI:10.1109/43.59070]
29. [29] M. A. Elgamel, M. Bayoumi, "On low-power high-level synthesis using genetic algorithms," in Proc. of the 9th International Conference on Electronics, Circuits and Systems, 15-18 Sept. 2002, pp. 725-728.
30. [30] G. W. Grewal, T. C. Wilson, "An enhanced genetic algorithm for solving the high-level synthesis problems of scheduling, allocation, and binding," International Journal of Computational Intelligence and Applications, vol. 1, pp. 91-110, 2001. [DOI:10.1142/S1469026801000044]
31. [31] V. Krishnan, S. Katkoori, "A genetic algorithm for the design space exploration of datapaths during high-level synthesis," IEEE Trans. Evol. Comput, vol. 10, no. 3, pp. 213-229, 2006. [DOI:10.1109/TEVC.2005.860764]
32. [32] A. Sengupta, R. Sedaghat, "Integrated scheduling, allocation and binding in high level synthesis using multi structure Genetic Algorithm based design space exploration," in Proc. of the 12th International Symposium on Quality Electronic Design, 14-16 March 2011, pp. 1-9. [DOI:10.1109/ISQED.2011.5770772] [PMCID]
33. [33] C. Pilato, D. Loiacono, A. Tumeo, F. Ferrandi, P. L. Lanzi, D. Sciuto, "Speeding-up expensive evaluations in high-level synthesis using solution modeling and fitness inheritance," in Computational Intelligence in Expensive Optimization Problems, vol. 2, 2010, pp. 701-723. [DOI:10.1007/978-3-642-10701-6_26]
34. [34] R. F. Abdel-kader, "Particle Swarm Optimization for Constrained Instruction Scheduling," VLSI design, vol. 2008, no. 4, January 2008. [DOI:10.1155/2008/930610]
35. [35] S. A. Hashemi, B. Nowrouzian, "A novel particle swarm optimization for high-level synthesis of digital filters," In Proc. of the 25th IEEE International Symposium on Circuits and Systems, 20-23 May 2012, pp. 580-583. [DOI:10.1109/ISCAS.2012.6272097]
36. [36] A. Sengupta, S. Bhadauria, S. P. Mohanty, "TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 655-668, April 2017. [DOI:10.1109/TCAD.2016.2597232]
37. [37] S. Bhadauria, A. Sengupta, "Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis," Applied Mathematics and Computation, vol. 269, pp. 265-278, Oct. 2015. [DOI:10.1016/j.amc.2015.07.042]
38. [38] S. Rajmohan, N. Ramasubramanian, "A Memetic Algorithm based Design Space Exploration for Datapath Resource Allocation during High Level Synthesis," Journal of Circuits, Systems and Computers, 2019. [DOI:10.1142/S0218126620500012]
39. [39] S. Rajmohan, N. Ramasubramanian, "Group influence based improved firefly algorithm for Design Space Exploration of Datapath resource allocation," Applied Intelligence, vol. 49, no. 6, pp. 2084-2100, June 2019. [DOI:10.1007/s10489-018-1371-3]
40. [40] C. Pilato, S. Garg, K. Wu, R. Karri, F. Regazzoni, "Securing Hardware Accelerators: A New Challenge for High-Level Synthesis," IEEE Embedded Systems Letters, vol. 10, no. 3, pp. 77-80, Sept. 2018. [DOI:10.1109/LES.2017.2774800]
41. [41] R. Nane et al., "A Survey and Evaluation of FPGA High-Level Synthesis Tools," IEEE Transactions on Computer-Aided Designe of Integrated Circuits and Systems, vol. 35, no. 10, pp. 1591-1604, Oct. 2016. [DOI:10.1109/TCAD.2015.2513673]
42. [42] N. S. Kim, J. Xiong, W. W. Hwu, "Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era," IEEE Micro, vol. 37, no. 4, pp. 10-18, 2017. [DOI:10.1109/MM.2017.3211105]
43. [43] D. R. R. Freias, A. V. M. Inocencio, L. T. Lins, G. J. Alves, M. A. Bendetti, "A Parallel Implementation of the Discrete Wavelet Transform Applied to Real-Time EEG Signal Filtering," in XXVI Brazilian Congress on Biomedical Engineering, May 2019, pp. 17-23. [DOI:10.1007/978-981-13-2517-5_3]
44. [44] C. Y. Pang, R. G. Zhou, B. Q. Hu, W. Hu, A. El-Rafei, "Signal and image compression using quantum discrete cosine transform," Information Science, vol. 473, pp. 121-141, January 2019. [DOI:10.1016/j.ins.2018.08.067]
45. [45] V. Mahale, M. M. H. Ali, P. L. Yannawar, A. Gaikwad, "Analysis of Image Inconsistency Based on Discrete Cosine Transform (DCT)," in Proc. of Information and Communictuin Technology for Intelligent Systems, Dec. 2018, vol. 1, pp. 563-571. [DOI:10.1007/978-981-13-1742-2_56]
46. [46] A. N. Serov, A. A. Shatokhin, G. V. Antipov, "Sample Rate Converter As a Means of Reducing Measurement Error of the Voltage Spectrum by Application of FFT," in Proc. of 29th International Conference Radioelektronika (RADIOELEKTRONIKA), June. 2019. [DOI:10.1109/RADIOELEK.2019.8733554] [PMID]
47. [47] S. G. Maghrebi, F. K. Deylamani, "Using WPT as a New Method Instead of FFT for Improving the Performance of OFDM Modulation," Signal and Data Processing, vol. 16, no. 2, pp. 121-136, 2019. [DOI:10.29252/jsdp.16.2.121]
48. [48] M. R. Esmaeili, SH. Zahiri, "Epileptic seizure detection using Inclined Planes system Optimization algorithm (IPO)," Signal and Data Processing, vol. 13, no. 4, pp. 29-42, 2017. [DOI:10.18869/acadpub.jsdp.13.4.29]
49. [49] S. P. Mohanty, N. Ranganathan, E. Kougianos, P. Patra, Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. Springer US, India 2008.
50. [50] S. Mirjalili, "Moth-flame optimization algorithm: A novel nature-inspired heuristic paradigm," in Knowledge-Based Systems, vol. 89, pp. 228-249, Nov. 2015. [DOI:10.1016/j.knosys.2015.07.006]
51. [51] J. Kennedy and R. Eberhart, "Particle swarm optimization," in Proc. of IEEE Neural Networks, 1995, pp. 1942-1948.
52. [52] M. Jhamb, Garima, H. Loohani, "Design, implementation and performance comparison of multiplier topologies in power-delay space," in Engineering Science and Technology, an International Journal, vol. 19, no. 1, pp. 355-363, March 2016. [DOI:10.1016/j.jestch.2015.08.006]
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