Volume 19, Issue 1 (5-2022)                   JSDP 2022, 19(1): 43-58 | Back to browse issues page


XML Persian Abstract Print


Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Dehghani A, RahimiZadeh K. Design of a novel congestion-aware communication mechanism for wireless NoC in multicore systems. JSDP 2022; 19 (1) : 4
URL: http://jsdp.rcisp.ac.ir/article-1-1077-en.html
Yasouj University
Abstract:   (1113 Views)
Network-on-Chip (NoC) has emerged as leading interconnection backbone to integrate numerous blocks in a single chip. Although it offers a high-performance communication infrastructure by using integrated switch-based networks, the possible performance improvement of a conventional NoC is restricted by multi-hop communications due to high transmission latency and power consumption incurred by the data transmission between two distant cores.  In order to mitigate this problem, wireless NoC (WNoC) architecture has proposed as an alternative solution to design flexible, low-power, and high bandwidth communication infrastructures for the future multicore platforms. It is necessary to mention that wire-based interconnections are still highly effective for short distances communications. Therefore, hybrid WNoC architectures are emerged as scalable communication structure to alleviate the deficits of traditional NOC architecture for the modern multicore systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing cores. However, sharing links between cores increases congestion in the network that limits the performance and scalability of NoCs and affects the system to work at less than its peak gain. Moreover, the congestion can heightens network inefficiency when the network is scaled to more nodes. In this paper, we propose a novel congestion-aware mesh-based WNoC architecture to address these issues. We consider optimization of the system cost and performance, simultaneously. For congestion control, it is recommended to include a multi-path routing. This means that several routes are calculated and recorded for each destination and finally the traffic load is distributed. Paths are selected based on their scores, which are obtained dynamically. When a path is used to transmit packets, the score of that path is reduced so that fewer packets are sent from that path and more scored paths are used. This approach aims to the distribution of traffic loads on the paths. The performance of the proposed architecture has been evaluated and compared with notable WNoC architectures through comprehensive simulations. The experimental results demonstrated the effectiveness of the proposed design under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption.
Article number: 4
Full-Text [PDF 1785 kb]   (464 Downloads)    
Type of Study: Research | Subject: Paper
Received: 2019/09/28 | Accepted: 2020/08/18 | Published: 2022/06/22 | ePublished: 2022/06/22

References
1. [1] "2013 ITRS Edition." [Online]. Available: http://www.itrs.net/Links/2013ITRS/Home2013.htm. [Accessed: 02-Mar-2019].
2. [2] A. Rezaei, M. Daneshtalab, F. Safaei, and D. Zhao, "Hierarchical approach for hybrid wireless Network-on-chip in many-core era," Comput. Electr. Eng., vol. 51, pp. 225-234, Apr. 2016. [DOI:10.1016/j.compeleceng.2015.10.007]
3. [3] P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2005. [DOI:10.1109/TC.2005.134]
4. [4] A. Shacham, K. Bergman, and L. P. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors," IEEE Trans. Comput., vol. 57, no. 9, pp. 1246-1260, Sep. 2008. [DOI:10.1109/TC.2008.78]
5. [5] D. W. Matolak, A. Kodi, S. Kaya, D. Ditomaso, S. Laha, and W. Rayess, "Wireless networks-on-chips: Architecture, wireless channel, and devices," IEEE Wirel. Commun., vol. 19, no. 5, pp. 58-65, Oct. 2012. [DOI:10.1109/MWC.2012.6339473]
6. [6] A. B. Kaplan, "Architectural Integration of RF-Interconnect to Enhance On-Chip Communication for Many-Core Chip Multiprocessors", PhD Thesis, Dept. of Computing Science, University of California, Los Angeles, 2008.
7. [7] D. DiTomaso, A. Kodi, D. Matolak, S. Kaya, S. Laha, and W. Rayess, "A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors," IEEE Trans. Parallel Distrib. Syst., vol. 26, no. 12, pp. 3289-3302, Dec. 2015. [DOI:10.1109/TPDS.2014.2383384]
8. [8] K. Chang et al., "Performance evaluation and design trade-offs for wireless network-on-chip architectures," ACM J. Emerg. Technol. Comput. Syst., vol. 8, no. 3, pp. 1-25, Aug. 2012. [DOI:10.1145/2287696.2287706]
9. [9] S. H. Gade and S. Deb, "HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures," IEEE Trans. Comput., vol. 66, no. 7, pp. 1145-1158, Jul. 2017. [DOI:10.1109/TC.2016.2643668]
10. [10] A. Ganguly, K. Chang, S. Deb, P. P. Pande, B. Belzer, and C. Teuscher, "Scalable hybrid wireless network-on-chip architectures for multicore systems," IEEE Trans. Comput., vol. 60, no. 10, pp. 1485-1502, Oct. 2011. [DOI:10.1109/TC.2010.176]
11. [11] A. Rezaei, M. Daneshtalab, M. Palesi, and D. Zhao, "Efficient Congestion-Aware Scheme for Wireless on-Chip Networks," in 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2016, pp. 742-749. [DOI:10.1109/PDP.2016.88]
12. [12] C. Wang, W. H. Hu, and N. Bagherzadeh, "A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms," Microprocess. Microsyst., vol. 36, no. 7, pp. 555-570, Oct. 2012. [DOI:10.1016/j.micpro.2011.10.002]
13. [13] B. A. Floyd, C. M. Hung, and K. K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002. [DOI:10.1109/4.997846]
14. [14] D. Zhao and Y. Wang, "SD-MAC: Design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip," IEEE Trans. Comput., vol. 57, no. 9, pp. 1230-1245, Sep. 2008. [DOI:10.1109/TC.2008.86]
15. [15] D. Zhao, Y. Wang, J. Li, and T. Kikkawa, "Design of multi-channel wireless NoC to improve on-chip communication capacity!," in Proceedings of the Fifth ACM/IEEE International Symposium, 2011, pp. 177-184. [DOI:10.1145/1999946.1999975] [PMCID]
16. [16] S. B. Lee et al., "A scalable micro wireless interconnect structure for CMPs," in Proceedings of the 15th annual international conference on Mobile computing and networking - MobiCom '09, 2009, pp. 217. [DOI:10.1145/1614320.1614345]
17. [17] D. DiTomaso, A. Kodi, S. Kaya, and D. Matolak, "IWISE: Inter-router wireless scalable express channels for Network-on-Chips (NoCs) architecture," in Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects, 2011, pp. 11-18. [DOI:10.1109/HOTI.2011.12]
18. [18] A. Dehghani and K. Jamshidi, "A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms," J. Supercomput., vol. 71, no. 8, 2015. [DOI:10.1007/s11227-015-1430-z]
19. [19] S. Deb et al., "Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects," IEEE Trans. Comput., vol. 62, no. 12, pp. 2382-2396, Dec. 2013. [DOI:10.1109/TC.2012.224]
20. [20] A. Dehghani and K. Jamshidi, "A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures," J. Emerg. Technol. Comput. Syst., vol. 12, no. 4, pp. 45:1--45:37, Mar. 2016. [DOI:10.1145/2814572]
21. [21] R. G. Kim et al., "Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs," IEEE Trans. Comput., vol. 65, no. 4, pp. 1323-1336, Apr. 2016. [DOI:10.1109/TC.2015.2441721]
22. [22] J. Murray, R. Kim, P. Wettin, P. P. Pande, and B. Shirazi, "Performance evaluation of congestion-aware routing with DVFS on a millimeter-wave small-world wireless NoC," ACM J. Emerg. Technol. Comput. Syst., vol. 11, no. 2, Oct. 2014. [DOI:10.1145/2644816]
23. [23] R. Kim, J. Murray, P. Wettin, P. P. Pande, and B. Shirazi, "An energy-efficient millimeter-wave wireless NoC with congestion-aware routing and DVFS," in Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, 2015, pp. 192-193. [DOI:10.1109/NOCS.2014.7008789]
24. [24] Y. Ouyang, Z. Li, K. Xing, Z. Huang, H. Liang, and J. Li, "Design of Low-Power WiNoC with Congestion-Aware Wireless Node," J. Circuits, Syst. Comput., vol. 27, no. 9, Aug. 2018. [DOI:10.1142/S0218126618501487]
25. [25] U. Y. Ogras and R. Marculescu, "'It's a small world after all': NoC performance optimization via long-range link insertion," IEEE Trans. Very Large Scale Integr. Syst., vol. 14, no. 7, pp. 693-706, Jul. 2006. [DOI:10.1109/TVLSI.2006.878263]
26. [26] P. Wettin, A. Vidapalapati, A. Gangul, and P. P. Pande, "Complex network-enabled robust wireless network-on-chip architectures," ACM J. Emerg. Technol. Comput. Syst., vol. 9, no. 3, pp. 1-19, Sep. 2013. [DOI:10.1145/2491676]
27. [27] S. Cahon, N. Melab, and E.-G. Talbi, "ParadisEO: A Framework for the Reusable Design of Parallel and Distributed Metaheuristics," J. Heuristics, vol. 10, no. 3, pp. 357-380, May 2004. [DOI:10.1023/B:HEUR.0000026900.92269.ec]
28. [28] G. M. Chiu and G. Ming, "The odd-even turn model for adaptive routing," IEEE Trans. Parallel Distrib. Syst., vol. 11, no. 7, pp. 729-738, Jul. 2000. [DOI:10.1109/71.877831]
29. [29] O. Lysne, T. Skeie, S. A. Reinemo, and I. Theiss, "Layered routing in irregular networks," IEEE Trans. Parallel Distrib. Syst., vol. 17, no. 1, pp. 51-65, Jan. 2006. [DOI:10.1109/TPDS.2006.12]
30. [30] R. K. V. Maeda et al., "JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models," in Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems - AISTECS '16, 2016, pp. 1-6. [DOI:10.1145/2857058.2857066]
31. [31] R. Manevich, L. Polishuk, I. Cidon, and A. Kolodny, "Designing single-cycle long links in hierarchical NoCs," Microprocess. Microsyst., vol. 38, no. 8, pp. 814-825, Nov. 2014. [DOI:10.1016/j.micpro.2014.05.005]
32. [32] R. K. V. Maeda, Q. Cai, J. Xu, Z. Wang, and Z. Tian, "Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance," in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, pp. 145-156. [DOI:10.1109/HPCA.2017.11] [PMID] [PMCID]
33. [33] A. B. Kahng, B. L. Bin Li, L.-S. P. L.-S. Peh, and K. Samadi, "ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration," 2009 Des. Autom. Test Eur. Conf. Exhib., pp. 1-6, Apr. 2009. [DOI:10.1109/DATE.2009.5090700]
34. [34] J. Mohebbi, M. Moradi, B. Salami, "Proposed Feature Selection for Dynamic Thermal Management in Multicore Systems," Signal and Data Processing, . vol. 16, no 1, pp. 125-142, 2019. http://jsdp.rcisp.ac.ir/article-1-801-fa.html. [DOI:10.29252/jsdp.16.1.125]

Add your comments about this article : Your username or Email:
CAPTCHA

Send email to the article author


Rights and permissions
Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

© 2015 All Rights Reserved | Signal and Data Processing